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solomon systech semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notice. http://www.solomon-systech.com ssd1800 series rev 1.0 p 1/42 mar 2004 copyright ? 2004 solomon systech limited advance information 80x16 + 1 icon line lcd segment / common driver with controller for character display system ssd1800
solomon systech mar 2004 p 2/42 rev 1.0 ssd1800 series table of contents 1 general description ......................................................................................................... ........ 5 2 features ..................................................................................................................... .................... 5 3 ordering information......................................................................................................... ...... 5 4 block diagram ................................................................................................................ ............. 6 5 pin arrangement of ssd1800z gold bump die .................................................................. 7 6 pin arrangement of SSD1800AV bare die ......................................................................... 10 7 pin descriptions ............................................................................................................. ........... 12 8 functional block descriptions ......................................................................................... 15 9 voltage generator circuit ................................................................................................. 24 10 frame frequency ............................................................................................................. ......... 25 11 command table ............................................................................................................... ........... 26 12 command descriptions ........................................................................................................ ... 28 13 maximum ratings............................................................................................................. ........... 33 14 dc characteristics.......................................................................................................... ........ 34 15 ac characteristics.......................................................................................................... ........ 35 16 application examples ........................................................................................................ ..... 38
ssd1800 series rev 1.0 p 3/42 mar 2004 solomon systech table of tables table 1 - ordering information ................................................................................................. ................. 5 table 2 - ssd1800z gold bump die pad coordinates ............................................................................ 8 table 3 - SSD1800AV bare die pad coordinates................................................................................... 11 table 4 - relationship between iconram address and display pattern ........................................... 18 table 5 - cgrom character code ................................................................................................. .......... 19 table 6 - relationship between character code (ddram) and character pattern (cgram)........... 20 table 7- contrast control register ............................................................................................. ............ 22 table 8 - command table........................................................................................................ ................. 26 table 9 - dd/ cgram address mapping ............................................................................................ .... 31 table 10 - iconram address mapping ............................................................................................. ..... 32 table 11 - maximum ratings (voltage reference to vss) .................................................................... 33 table 12 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, ta = -30 to 85c.).................................................................................................... ... 34 table 13 - ac characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, ta = -30 to 85c.).................................................................................................... ... 35 table 14 - 6800-series mpu parallel interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c)................................................................................................................... ............ 35 table 15 - 8080-series mpu parallel interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c)................................................................................................................... ............ 36 table 16 - serial interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c) ....... 37
solomon systech mar 2004 p 4/42 rev 1.0 ssd1800 series table of figures figure 1 - block diagram of ssd1800............................................................................................ ........... 6 figure 2 - ssd1800z pin arrangement ............................................................................................ ......... 7 figure 3 - SSD1800AV pin arrangement ........................................................................................... ..... 10 figure 4 - timing diagram of 8-bit parallel bus mode data transfer (6800 mpu mode) ................... 16 figure 5 - timing diagram of 8-bit parallel bus mode data transfer (8080 mpu mode) ................... 16 figure 6 - timing diagram of 4-bit parallel bus mode data transfer (6800 mpu mode) ................... 17 figure 7 - timing diagram of 4-bit parallel bus mode data transfer (8080 mpu mode) ................... 17 figure 8 - timing diagram of serial data transfer .............................................................................. .. 17 figure 9 - ddram address ....................................................................................................... ............... 18 figure 10 - configurations for dc-dc converter................................................................................. .. 21 figure 11 - configurations for voltage regulator ............................................................................... .. 21 figure 12 - when built-in power supply is used ................................................................................. .. 24 figure 13 - when external power supply is used ................................................................................. 24 figure 14 - function set command (x1x0 = 00) ................................................................................... .. 28 figure 15 - com0 ~ com15 is a double height line in function set command (x1x0 = 01)............. 28 figure 16 - display attributes ................................................................................................. ................. 30 figure 17 - 6800-series mcu parallel interface waveform.................................................................... 35 figure 18 - 8080-series mcu parallel interface waveform.................................................................... 36 figure 19 - serial interface characteristics ................................................................................... ......... 37 figure 20- application circuit: external regulator with internal divider mode (8-bit 6800 mode)... 38 figure 21 - application circuit: all internal power mode with 2x regulated dc-dc converter (serial mode).................................................................................................................. ..................... 39 figure 22- application circuit: all internal power mode with 3x regulated dc-dc converter (8-bit 8080 mode) ..................................................................................................................... .................... 40 figure 23- recommended initializing of ssd1800............................................................................ 41
ssd1800 series rev 1.0 p 5/42 mar 2004 solomon systech 1 general description ssd1800 is a single-chip cmos lcd driver with controller for liquid crystal dot-matrix character display system. it consists of 97 high voltage driving output pins for driving 80 segments, 16 commons and 1 icon driving-common. it can display 2 lines of 16 characters with 5x8 dots format. the double height character mode and line vertical scroll functions are supported. ssd1800 displays character directly from its internal 10,240 bits (256 characters x 5 x 8 dots) character generator rom (cgrom). all the character codes are stored in the 512 bits (16 characters x 4 lines) data display ram (ddram). user defined character can be loaded via 320 bits (8 characters x 5 x 8 dots) character generator ram (cgram). in addition, there is a 80 bits icon ram for icon display. data/ commands are sent from general mcu through software selectable 6800-/8080-series compatible 4/ 8-bit parallel interface or serial peripheral interface. ssd1800 embeds a dc-dc converter, voltage regulator, voltage divider and rc oscillator that reduce the number of external components. with the special design on minimizing power consumption and die size, ssd1800 is suitable for portable battery-driven applications requiring a long operation period and a compact size. 2 features single supply operation, 2.4v - 3.6v maximum 5.8v lcd driving output voltage low current sleep mode on-chip 2x/3x dc-dc converter/ external power supply on-chip rc oscillator/ external clock on-chip voltage regulator on-chip voltage divider with programmable bias ratio (1/4, 1/5) 32 level internal contrast control 2 lines x 16 characters with 5x8 dots format display and 80 icons double height character mode, blink mode, cursor display and line vertical scroll functions row remapping and column remapping (4-type lcd application available) 8/4-bit 6800-series parallel interface, 8/4-bit 8080-series parallel interface and serial peripheral interface 256 build in characters and 8 user defined characters on-chip memories character generator rom (cgrom): 10240 bits (256 characters x 5 x 8 dots) character generator ram (cgram): 320 bits (8 characters x 5 x 8 dots) display data ram (ddram): 512 bits (16 characters x 4 lines) segment icon ram (iconram): 80 bits (80 icons) available in bare die/gold bumped die 3 ordering information table 1 - ordering information ordering part number display size package form reference remark ssd1800z 16x2 characters gold-bump die figure 2 on page 7 - SSD1800AV 16x2 characters bare die figure 3 on page 10 -
solomon systech mar 2004 p 6/42 rev 1.0 ssd1800 series 4 block diagram a v dd & dv dd a v ss & dv ss internal mi comi0, comi com0~ com15 seg0~seg79 hv buffer cell ( level shifter ) dis p la y data latch oscillato r dis p la y timin g generato r level selecto r re g ulated dc/dc converter, volta g e divider, contrast control command interface parallel/ serial interface command decode r character generator rom (cgrom) character generator ram (cgram) display data ram (ddram) icon ram (iconram) cursor and bli k control v l2 v l3 v l4 v l5 v l6 v f c 1p c 1n c 2p c 2n d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (sck) (sda) dirs c68/ 80 r/ w e d/ c (wr) ( rd) cs p/ s res dl clk res reset circuit figure 1 ? block diagram of ssd1800
ssd1800 series rev 1.0 p 7/42 mar 2004 solomon systech 5 pin arrangement of ssd1800z gold bump die alignment keys figure 2 - ssd1800z pin arrangement die size: 6170um x 1480um (include scribe line) 6070um x 1380um (exclude scribe line) die thickness: 670 +/-25um bump size minimum pitch pad: 1-63 52.15 x 60.2 um 76.3um pad: 65-79, 164-178 74.9 x 42 um 63.7um pad: 81-162 42 x 74.9 um 63.7um pad: 64,80,163,179 52.15 x 52.15 um bump height: nominal 18um note: 1. pads: 35-36, 45, 64-65, 75-81, 162-164, 166-169, 178-179 nc pads. 2. the die faces up in the diagram. 3. coordinates are reference to the center of the chip. 4. unit of coordinates and size of all alignment keys are in um. 5. all alignment keys do not contain gold bump. (-2835, -598.5) x 37.6 m 8.75 m (2835, -598.5) x 37.6 m 8.75 m 26.3 m 26.3 m 26.3 m x center (-2940.9, 480.0) 26.3 m 26.3 m 26.3 m 26.3 m 52.5 m x center (2940.9, 480.0) 26.3 m 26.3 m 26.3 m 13.1 m 61.3 m 61.3 m 88 13.1 m center (-2101.9, 169.6) x
solomon systech mar 2004 p 8/42 rev 1.0 ssd1800 series table 2 - ssd1800z gold bump die pad coordinates pad# name x y pad# name x y 1 d/ c -2401.53 -600.78 41 c1n 684.78 -600.78 2 dvss -2325.23 -600.78 42 c1n 761.08 -600.78 3 r/ w( wr ) -2248.93 -600.78 43 c1p 837.38 -600.78 4 dvdd -2172.63 -600.78 44 c1p 913.68 -600.78 5 e( rd ) -2096.33 -600.78 45 nc 989.98 -600.78 6 cs -2020.03 -600.78 46 dvss 1080.63 -600.78 7 d7 -1943.73 -600.78 47 avss 1156.93 -600.78 8 d6 -1867.43 -600.78 48 dvss 1233.23 -600.78 9 d5 -1791.13 -600.78 49 ref 1309.53 -600.78 10 d4 -1714.83 -600.78 50 dirs 1385.83 -600.78 11 d3 -1638.53 -600.78 51 dvdd 1462.13 -600.78 12 d2 -1562.23 -600.78 52 avdd 1538.43 -600.78 13 d1 -1485.93 -600.78 53 dvdd 1614.73 -600.78 14 d0 -1409.63 -600.78 54 clk 1691.03 -600.78 15 dvdd -1333.33 -600.6 55 vss 1767.33 -600.78 16 avdd -1257.03 -600.6 56 p / s 1843.63 -600.78 17 dvdd -1180.73 -600.6 57 dvdd 1919.93 -600.78 18 dvss -1104.43 -600.78 58 dl 1996.23 -600.78 19 avss -1028.13 -600.6 59 dvss 2072.53 -600.78 20 dvss -951.83 -600.6 60 c68/( 80 ) 2148.83 -600.78 21 vl2 -861.18 -600.6 61 dvdd 2225.13 -600.78 22 vl2 -784.88 -600.6 62 res 2301.43 -600.78 23 vl3 -708.58 -600.6 63 test 2377.73 -600.78 24 vl3 -632.28 -600.78 64 nc 2939.3 -600.78 25 vl4 -555.98 -600.78 65 nc 2939.3 -520.1 26 vl4 -479.68 -600.78 66 comi0 2939.3 -456.4 27 vl5 -403.38 -600.78 67 com 0 2939.3 -392.7 28 vl5 -327.08 -600.78 68 com 1 2939.3 -329 29 vl6 -246.05 -600.78 69 com 2 2939.3 -265.3 30 vl6 -169.75 -600.78 70 com 3 2939.3 -201.6 31 vl6 -93.45 -600.78 71 com 4 2939.3 -137.9 32 vl6 -17.15 -600.78 72 com 5 2939.3 -74.2 33 vf 64.75 -600.78 73 com 6 2939.3 -10.5 34 vf 141.05 -600.78 74 com 7 2939.3 53.2 35 nc 222.25 -600.78 75 nc 2939.3 116.90 36 nc 298.55 -600.78 76 nc 2939.3 180.6 37 c2n 379.58 -600.78 77 nc 2939.3 244.3 38 c2n 455.88 -600.78 78 nc 2939.3 308.0 39 c2p 532.18 -600.78 79 nc 2939.3 371.7 40 c2p 608.48 -600.78 80 nc 2939.3 593.43
ssd1800 series rev 1.0 p 9/42 mar 2004 solomon systech pad# name x y pad# name x y 81 nc 2579.85 593.43 131 seg49 -605.15 593.43 82 seg0 2516.15 593.43 132 seg50 -668.85 593.43 83 seg1 2452.45 593.43 133 seg51 -732.55 593.43 84 seg2 2388.75 593.43 134 seg52 -796.25 593.43 85 seg3 2325.05 593.43 135 seg53 -859.95 593.43 86 seg4 2261.35 593.43 136 seg54 -923.65 593.43 87 seg5 2197.65 593.43 137 seg55 -987.35 593.43 88 seg6 2133.95 593.43 138 seg56 -1051.05 593.43 89 seg7 2070.25 593.43 139 seg57 -1114.75 593.43 90 seg8 2006.55 593.43 140 seg58 -1178.45 593.43 91 seg9 1942.85 593.43 141 seg59 -1242.15 593.43 92 seg10 1879.15 593.43 142 seg60 -1305.85 593.43 93 seg11 1815.45 593.43 143 seg61 -1369.55 593.43 94 seg12 1751.75 593.43 144 seg62 -1433.25 593.43 95 seg13 1688.05 593.43 145 seg63 -1496.95 593.43 96 seg14 1624.35 593.43 146 seg64 -1560.65 593.43 97 seg15 1560.65 593.43 147 seg65 -1624.35 593.43 98 seg16 1496.95 593.43 148 seg66 -1688.05 593.43 99 seg17 1433.25 593.43 149 seg67 -1751.75 593.43 100 seg18 1369.55 593.43 150 seg68 -1815.45 593.43 101 seg19 1305.85 593.43 151 seg69 -1879.15 593.43 102 seg20 1242.15 593.43 152 seg70 -1942.85 593.43 103 seg21 1178.45 593.43 153 seg71 -2006.55 593.43 104 seg22 1114.75 593.43 154 seg72 -2070.25 593.43 105 seg23 1051.05 593.43 155 seg73 -2133.95 593.43 106 seg24 987.35 593.43 156 seg74 -2197.65 593.43 107 seg25 923.65 593.43 157 seg75 -2261.35 593.43 108 seg26 859.95 593.43 158 seg76 -2325.05 593.43 109 seg27 796.25 593.43 159 seg77 -2388.75 593.43 110 seg28 732.55 593.43 160 seg78 -2452.45 593.43 111 seg29 668.85 593.43 161 seg79 -2516.15 593.43 112 seg30 605.15 593.43 162 nc -2579.85 593.43 113 seg31 541.45 593.43 163 nc -2939.3 593.43 114 seg32 477.75 593.43 164 nc -2939.3 371.7 115 seg33 414.05 593.43 165 comi1 -2939.3 308 116 seg34 350.35 593.43 166 nc -2939.3 244.3 117 seg35 286.65 593.43 167 nc -2939.3 180.6 118 seg36 222.95 593.43 168 nc -2939.3 116.9 119 seg37 159.25 593.43 169 nc -2939.3 53.2 120 seg38 95.55 593.43 170 com15 -2939.3 -10.5 121 seg39 31.85 593.43 171 com14 -2939.3 -74.2 122 seg40 -31.85 593.43 172 com13 -2939.3 -137.9 123 seg41 -95.55 593.43 173 com12 -2939.3 -201.6 124 seg42 -159.25 593.43 174 com11 -2939.3 -265.3 125 seg43 -222.95 593.43 175 com10 -2939.3 -329 126 seg44 -286.65 593.43 176 com9 -2939.3 -392.7 127 seg45 -350.35 593.43 177 com8 -2939.3 -456.4 128 seg46 -414.05 593.43 178 nc -2939.3 -520.1 129 seg47 -477.75 593.43 179 nc -2939.3 -600.78 130 seg48 -541.45 593.43
solomon systech mar 2004 p 10/42 rev 1.0 ssd1800 series 6 pin arrangement of SSD1800AV bare die figure 3 - SSD1800AV pin arrangement die size: 6260um x 1810um (include scribe line) die thickness: 670 +/-25um pad metal size: 88 x 88um pad opening size: 80 x 80um pad number pad metal size pads: 1-9, 48-56, 72-80, 119-127 103um x111um pads: 57, 58, 70, 71, 128, 129, 141, 142 111um x103um pads: 10-47, 81-118 90um x111um pads: 59-69, 130-140 111um x90um note: 1. pads: 1,2, 29, 34, 56-59, 141, 142 are nc pads. 2. the die faces up in the diagram. 3. coordinates are reference to the center of the chip.
ssd1800 series rev 1.0 p 11/42 mar 2004 solomon systech table 3 - SSD1800AV bare die pad coordinates pad # name x y pad # name x y pad # name x y 1 nc -2748.20 -772.71 51 com3 2198.53 -772.71 101 seg41 -145.08 772.98 2 nc -2638.13 -772.71 52 com4 2308.60 -772.71 102 seg42 -239.93 772.98 3 com15 -2528.05 -772.71 53 com5 2418.68 -772.71 103 seg43 -334.78 772.98 4 com14 -2417.98 -772.71 54 com6 2528.75 -772.71 104 seg44 -429.63 772.98 5 com13 -2307.90 -772.71 55 com7 2638.83 -772.71 105 seg45 -524.48 772.98 6 com12 -2197.83 -772.71 56 nc 2748.90 -772.71 106 seg46 -619.33 772.98 7 com11 -2087.75 -772.71 57 nc 2998.10 -687.75 107 seg47 -714.18 772.98 8 com10 -1977.68 -772.71 58 nc 2998.10 -577.68 108 seg48 -809.03 772.98 9 com9 -1867.60 -772.71 59 nc 2998.10 -467.60 109 seg49 -903.88 772.98 10 com8 -1757.53 -772.71 60 seg0 2998.10 -372.75 110 seg50 -998.73 772.98 11 d/ c -1662.68 -772.71 61 seg1 2998.10 -277.90 111 seg51 -1093.58 772.98 12 r/ w( wr ) -1567.83 -772.71 62 seg2 2998.10 -183.05 112 seg52 -1188.43 772.98 13 e( rd ) -1472.98 -772.71 63 seg3 2998.10 -88.20 113 seg53 -1283.28 772.98 14 cs -1378.13 -772.71 64 seg4 2998.10 6.65 114 seg54 -1378.13 772.98 15 d7 -1283.28 -772.71 65 seg5 2998.10 101.50 115 seg55 -1472.98 772.98 16 d6 -1187.73 -772.71 66 seg6 2998.10 196.35 116 seg56 -1567.83 772.98 17 d5 -1092.18 -772.71 67 seg7 2998.10 291.20 117 seg57 -1662.68 772.98 18 d4 -996.63 -772.71 68 seg8 2998.10 386.05 118 seg58 -1757.53 772.98 19 d3 -901.08 -772.71 69 seg9 2998.10 480.90 119 seg59 -1867.60 772.98 20 d2 -805.53 -772.71 70 seg10 2998.10 590.98 120 seg60 -1977.68 772.98 21 d1 -709.98 -772.71 71 seg11 2998.10 701.05 121 seg61 -2087.75 772.98 22 d0 -614.43 -772.71 72 seg12 2742.43 772.98 122 seg62 -2197.83 772.98 23 vl2 -519.58 -772.71 73 seg13 2632.35 772.98 123 seg63 -2307.90 772.98 24 vl3 -424.73 -772.71 74 seg14 2522.28 772.98 124 seg64 -2417.98 772.98 25 vl4 -329.88 -772.71 75 seg15 2412.20 772.98 125 seg65 -2528.05 772.98 26 vl5 -235.03 -772.71 76 seg16 2302.13 772.98 126 seg66 -2638.13 772.98 27 vl6 -140.18 -772.71 77 seg17 2192.05 772.98 127 seg67 -2748.20 772.98 28 vf -45.33 -772.71 78 seg18 2081.98 772.98 128 seg68 -2998.10 -687.75 29 nc 49.53 -772.71 79 seg19 1971.90 772.98 129 seg69 -2998.10 -577.68 30 c2n 144.38 -772.71 80 seg20 1861.83 772.98 130 seg70 -2998.10 -467.60 31 c2p 239.23 -772.71 81 seg21 1751.75 772.98 131 seg71 -2998.10 -372.75 32 c1n 334.08 -772.71 82 seg22 1657.08 772.98 132 seg72 -2998.10 -277.90 33 c1p 428.93 -772.71 83 seg23 1562.23 772.98 133 seg73 -2998.10 -183.05 34 nc 523.78 -772.71 84 seg24 1467.38 772.98 134 seg74 -2998.10 -88.20 35 avss 618.63 -772.71 85 seg25 1372.53 772.98 135 seg75 -2998.10 6.65 36 dvss 713.48 -772.71 86 seg26 1277.68 772.98 136 seg76 -2998.10 101.50 37 ref 808.33 -772.71 87 seg27 1182.83 772.98 137 seg77 -2998.10 196.35 38 dirs 903.18 -772.71 88 seg28 1087.98 772.98 138 seg78 -2998.10 291.20 39 avdd 998.03 -772.71 89 seg29 993.13 772.98 139 seg79 -2998.10 386.05 40 dvdd 1092.88 -772.71 90 seg30 898.28 772.98 140 icons2 -2998.10 480.90 41 clk 1187.73 -772.71 91 seg31 803.43 772.98 141 nc -2998.10 590.98 42 p/ s 1282.58 -772.71 92 seg32 708.58 772.98 142 nc -2998.10 701.05 43 dl 1377.43 -772.71 93 seg33 613.73 772.98 44 c68/( 80 ) 1472.28 -772.71 94 seg34 518.88 772.98 45 res 1567.13 -772.71 95 seg35 424.03 772.98 46 test 1661.98 -772.71 96 seg36 329.18 772.98 47 icons1 1758.23 -772.71 97 seg37 234.33 772.98 48 com0 1868.30 -772.71 98 seg38 139.48 772.98 49 com1 1978.38 -772.71 99 seg39 44.63 772.98 50 com2 2088.45 -772.71 100 seg40 -50.23 772.98
solomon systech mar 2004 p 12/42 rev 1.0 ssd1800 series 7 pin descriptions 7.1 d/ c this pin is data/ command control pin. when the pin is pulled high, the data at d 7 -d 0 is treated as display data. when the pin is pulled low, the data at d 7 -d 0 will be transferred to the command register. 7.2 r/ w ( wr ) this pin is microprocessor interface input. when interfacing to a 6800-series microprocessor, this pin will be used as r/w signal input. read mode will be carried out when this pin is pulled high and write mode when low. when interfacing to a 8080-microprocessor, this pin will be the wr input. data write operation is initiated when this pin is pulled low and the chip is selected. this pin must be fixed to high or low in serial mode. 7.3 dvdd & avdd digital and analog power supply pin. 7.4 dvss & avss ground. 7.5 e( rd ) this pin is microprocessor interface input. when interfacing to a 6800-series microprocessor, this pin will be used as the enable signal, e. read/ write operation is initiated when this pin is pulled high and the chip is selected. when interfacing to a 8080-microprocessor, this pin receives the rd signal. data read operation is initiated when this pin is pulled low and the chip is selected. this pin must be fixed to high or low in serial mode. 7.6 cs this pin is the chip select input. 7.7 d 7 -d 0 these pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode. in 8-bit bus mode, d 7 is the msb while d 0 is the lsb. in 4-bit bus mode, it is needed to transfer 4-bit data (through d 7 -d 4 ) by two times. the high order bits (for 8-bit mode d 7 -d 4 ) are written before the low order bits (for 8-bit mode d 3 -d 0 ) in write transaction and low order bits (8-bit mode d 3 -d 0 ) are read before the high order bits (8-bit mode d 7 - d 4 ) in read transaction. the d 3 -d 0 pins must be fixed to high or low in 4-bit bus mode. after resets, ssd1800 considers first 4-bit data from mpu as the high order bits. when serial mode is selected, d 7 is the serial data input (sda) and d 6 is the serial clock input (sck). d5-d0 must be fixed to high or low in serial mode
ssd1800 series rev 1.0 p 13/42 mar 2004 solomon systech 7.7 v l6 , v l5, v l4 , v l3 , v l2 lcd driving voltages. they can be supplied externally or generated by the internal bias divider. they have the following relationship: v l6 > v l5 > v l4 > v l3 > v l2 > v ss 1:4 bias 1:5 bias (default) vl5 3/4 * vl6 4/5 * vl6 vl4 2/4 * vl6 3/5 * vl6 vl3 2/4 * vl6 2/5 * vl6 vl2 1/4 * vl6 1/5 * vl6 vl6 is the most positive lcd driving voltage. it can be supplied externally or generated by the internal regulator. it is recommended to add a capacitor between vl6 and vss for external regulator. 7.8 vf this pin is the input of the built-in voltage regulator. when external resistor network is selected to generate the lcd driving level, v l6 , two external resistors, r 1 and r 2 , are connected between av ss and v f , and v f and v l6 , respectively (see application circuit) 7.9 ref this pin is to select the input voltage of internal voltage regulator. this pin is need to pulled low for normal internal voltage regulator operation. 7.10 dirs this pin controls the direction of segment. when dirs = low seg0 -> seg2 -> ..... -> seg78 -> seg79 when dirs = high seg79 -> seg78 -> ..... -> seg1 -> seg0 7.11 clk external clock input. it must be fixed to high or low when the internal oscillation circuit is used. in case of the external clock mode, clk is used as the clock and osc bit should be off. 7.12 p/ s this pin is serial/ parallel interface selection input. when this pin is pulled high, parallel mode is selected. when it is pulled low, serial interface will be selected. read back operation is only available in parallel mode. 7.13 dl this pin is to select the data length for parallel data input. when p/ s = low dl = low or high: serial interface mode when p/ s = high dl = low: 4-bit bus mode dl = high: 8-bit bus mode this pin must be fixed to high or low in serial mode.
solomon systech mar 2004 p 14/42 rev 1.0 ssd1800 series 7.14 c68/ 80 this pin is microprocessor interface selection input. when the pin is pulled high, 6800 series interface is selected and when the pin is pulled low, 8080 series mcu interface is selected. this pin must be fixed to high or low in serial mode. 7.15 res this pin is reset signal input. initialization of the chip is started once this pin is pulled low. minimum pulse width for completing the reset is 10ms. 7.16 test test pin. this pin is not used for normal operation. leave this pin open (nc). 7.17 c 1p , c 1n , c 2p and c 2n when internal dc-dc voltage converter is used, external capacitors are connected between these pins. different connection will result in different dc-dc converter multiple factor, 2x/3x. details connections please refer to figure 12. 7.18 comi0, comi1 there are two icons pins (pin47 and 140). both pins output exactly the same signal. the reason for duplicating the pin is to enhance the flexibility of the lcd layout. 7.19 com0 ? com15 these pins provide the common driving signal com0 ? com15 to the lcd panel. their output voltage levels are av ss during sleep mode and standby mode. 7.20 seg0 - seg79 these pins provide the lcd segment driving signals. their output voltage levels are av ss during sleep mode and standby mode. 7.21 nc these are the no connection pins. nothing should be connected to these pins, nor they are connected together. these pins should be left open individually.
ssd1800 series rev 1.0 p 15/42 mar 2004 solomon systech 8 functional block descriptions 8.1 command decoder and command interface this module determines whether the input data is interpreted as data or command. data is directed to this module based upon the input of the d/ c pin. if d/ c is high, data is written to internal memories (ddram, cgram, iconram). if d/ c is low, the input at d 7 -d 0 is interpreted as a command and it will be decoded and be written to the corresponding command register. 8.2 mpu parallel 6800-series interface in 8 bits bus mode the parallel interface consists of 8 bi-directional data pins (d 7 -d 0 ), r/ w( wr ), d/ c, e( rd ), cs . r/ w( wr ) input high indicates a read operation from the internal ram (ddram, cgram and iconram). r/ w( wr ) input low indicates a write operation to internal ram (ddram, cgram and iconram) or internal command registers depending on the status of d/ c input. the e( rd ) input serves as data latch signal (clock) when high provided that cs are low. refer to figure 20 for parallel interface timing diagram of 6800-series microprocessors. in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processings are internally performed which require the insertion of a dummy read before the first actual display data read. this is shown in figure 4 below. the dummy read make the address counter (ac) increased by 1. so it is recommended to set address again before writing. the consecutive read after the dummy read are also the valid data. the instruction read cycle is not supported and it is regarded as a no operation cycle. 8.3 mpu parallel 8080-series interface in 8 bits bus mode the parallel interface consists of 8 bi-directional data pins (d 7 -d 0 ), r/ w( wr ), d/ c, e( rd ), cs . e( rd ) input serves as data read latch signal (clock) when low provided that cs is low whether it is command write or internal ram read/ write is controlled by d/ c. r/ w( wr ) input serves as data write latch signal (clock) when low provided that cs is low. refer to figure 21 for parallel interface timing diagram of 8080-series microprocessor. similar to 6800-series interface, a dummy read is also required before the first actual display data read. 8.4 4-bit mpu parallel 6800/8080-series interface the control of 4-bit bus mode is exactly the same as 8-bit bus mode except 2 consecutive access (read/ write) is needed to read/ write 8 bits data. for write operation, upper order bits are written before the low order bits, and low order bits are always read before the upper order bit in read transaction. 8.5 mpu serial interface the serial interface consists of serial clock sck (d 6 ), serial data sda (d 7 ), d/ c, cs . sda is shifted into a 8-bit shift register on every rising edge of sck in the order of d 7 , d 6 , ... d 0 . d/ c is sampled on every eighth clock to determine whether the data byte in the shift register is written to the internal ram (ddram, cgram, iconram) or command register at the same clock. 8.6 oscillator circuit this module is an on-chip low power rc oscillator circuitry. the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator.
solomon systech mar 2004 p 16/42 rev 1.0 ssd1800 series 8.7 address counter (ac) address counter (ac) in ssd1800 stores ddram/ cgram/ iconram address. after writing into or reading from ddram/ cgram/ iconram. ac is automatically increased by 1. there is only one address counter and stores the address among ddram / cgram / iconram. figure 4 - timing diagram of 8-bit parallel bus mode data transfer (6800 mpu mode) figure 5 - timing diagram of 8-bit parallel bus mode data transfer (8080 mpu mode) dl c68/80 cs d/c r/w (wr) e(rd) ram read dummy read nop instruction write data write d7 ~ d0 valid data dl ram read dummy read nop instruction write data write d7 ~ d0 c68/80 cs d/c r/w (wr) e(rd) valid data
ssd1800 series rev 1.0 p 17/42 mar 2004 solomon systech figure 6 - timing diagram of 4-bit parallel bus mode data transfer (6800 mpu mode) figure 7 - timing diagram of 4-bit parallel bus mode data transfer (8080 mpu mode) figure 8 ? timing diagram of serial data transfer dl c68/80 cs d/c r/w (wr) e(rd) upper 4-bits d7 ~ d0 ram dummy nop instruction write write read read data upper 4-bits lower 4-bits lower 4-bits upper 4-bits lower 4-bits dl cs d/c c68/80 e(rd) r/w (wr) upper 4-bits d7 ~ d0 ram dummy nop instruction write write read read data upper 4-bits lower 4-bits lower 4-bits upper 4-bits lower 4-bits cs d/c sda(d7) sck(d6) d7 d6 d5 d4 d3 d2 d1 d0 d7 1 2 3 4 5 6 7 8 9
solomon systech mar 2004 p 18/42 rev 1.0 ssd1800 series 8.8 display data ram (ddram) ddram stores display data of maximum 64 x 8 bits (max 64 characters). ddram address is set in the address counter as a hexadecimal number. figure 9 - ddram address 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 22 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 33 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 8.9 segment icon ram (iconram) iconram has segment control data and segment pattern data. there are 2 icons pins (comi0 & comi1), which have the same signal. so the icons on the same seg are displayed at the same time. the number of icons is 80. table 4 - relationship between iconram address and display pattern iconram bits iconram address d7 d6 d5 d4 d3 d2 d1 d0 00h - - - s0 s1 s2 s3 s4 01h - - - s5 s6 s7 s8 s9 02h - - - s10 s11 s12 s13 s14 ? ? ? ? ? ? ? ? ? 0dh - - - s65 s66 s67 s68 s69 0eh - - - s70 s71 s72 s73 s74 0fh - - - s75 s76 s77 s78 s79 note: ?-?: don?t care. 8.10 character generator rom (cgrom) cgrom has 5 x 8 dot 256 characters. the function set instruction selects the 8 characters (00h - 07h) of cgrom or cgram. 1 s t ch 16 th ch seg 0 seg 79 com0 ? com7 com8 ? com15 hidden line hidden line ( 1 ) ddram add r ess
ssd1800 series rev 1.0 p 19/42 mar 2004 solomon systech table 5 - cgrom character code note: the cgrom 0000xxxx are empty.
solomon systech mar 2004 p 20/42 rev 1.0 ssd1800 series 8.11 character generator ram (cgram) cgram has up to 5 x 8 dots 8 characters. by writing font data to cgram, user defined character can be used. cgram can be written regardless of function set instruction. table 6 - relationship between character code (ddram) and character pattern (cgram) iconram bits character code (ddram data) cgram address d7 d6 d5 d4 d3 d2 d1 d0 00h (pattern 0) 40h 41h 42h 43h 44h 45h 46h 47h - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 01h (pattern 1) 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 02h (pattern 2) 50h 51h 52h 53h 54h 55h 56h 57h - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 03h (pattern 3) 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 04h (pattern 4) 60h 61h 62h 63h 64h 65h 66h 67h - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 05h (pattern 5) 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
ssd1800 series rev 1.0 p 21/42 mar 2004 solomon systech character code (ddram data) cgram address iconram bits d7 d6 d5 d4 d3 d2 d1 d0 06h (pattern 6) 70h 71h 72h 73h 74h 75h 76h 77h - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 07h (pattern 7) 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x note: ?-? don?t use ?x? pattern 0 or 1 8.12 lcd driving voltage generator and regulator this module generates the lcd voltage required for display driving output. it takes a single supply input and generates necessary voltage levels. this block consists of: 1. 2x/3x dc-dc voltage converter the built-in regulated dc-dc voltage converter is used to generate positive lcd driving voltage with internal voltage reference, vref, relative to avss figure 10 ? configurations for dc-dc converter figure 11 - configurations for voltage regulator ssd1800 ssd1800 avdd c1p c1n c2p vl6 avdd c1p c1n c2p c2n vl6 c1 + + c2 + c2 c1 + + c2 c2 + avdd avdd 3x dc-dc converter 2x dc-dc converter remarks: c1 = 2.2 f - 4.7 f c2 = 0.1
solomon systech mar 2004 p 22/42 rev 1.0 ssd1800 series 2. voltage regulator the feedback gain control for lcd driving contrast can be adjusted by using reference voltage and external resistor network. the reference voltage is supplied by internal vref and ref should be connected to low for normal operation of internal voltage reference vref. the external resistors are required to be connected between av ss and v f (r1), and between v f and v l6 (r2). the following equations are used to calculate the regulator output voltages. 6 2 1 1 l ref r vv r ?? =+ ?? ?? and 06 . 0 2 = v v ref 3. contrast control software control of the 32 contrast voltage levels at each voltage regulator feedback gain. the equation of calculating the lcd driving voltage is given as: 6 2 11 1 150 l ref r n vv r ?? ? ? =+ ? ?? ? ? ?? ? ? where n is set in contrast control register. table 7- contrast control register no. x7 x6 x5 x4 x3 x2 x1 x0 n vl6 contrast 1 - - - 0 0 0 0 0 0 (default) maximum high 2 - - - 0 0 0 0 1 1 3 - - - 0 0 0 1 0 2 4 - - - 0 0 0 1 1 3 . . . . . . . . . - - - - - - - - - . . . . . . . . . . . . . . . . . . . . . . . . 31 - - - 1 1 1 1 0 30 . . 32 1 1 1 1 1 31 minimum low (? - ?: don?t care) 4. bias divider divide the regulator output to give the lcd driving voltages (v l5 -v l2 ). a low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. 5. bias ratio selection circuitry software control of 1/4 and 1/5 bias ratio to match the characteristic of lcd panel.
ssd1800 series rev 1.0 p 23/42 mar 2004 solomon systech 8.13 reset circuit this block includes power on reset circuitry and the reset pin res . both of these having the same reset function. once res receives a negative reset pulse, all internal circuitry will start to initialize. minimum pulse width for completing the reset sequence is 10ms. the status of the chip after reset is given by: 1. display/ cursor/ blink is turned off 2. 2-line display mode 3. power control register is set to 000b 4. oscillator is off 5. power save is off 6. cgram is not used 7. shift register data clear in serial interface 8. bias ratio is set to 1/5 9. address counter is set to 00h 10. normal scan direction of the com outputs 11. contrast control register is set to 00h 12. test mode is turned off 13. in case of 4-bit interface mode selection, ssd1800 considers the 1st 4-bit data from mpu as the high order bits. 14. the 1st line of display is the address 00h-0fh. 8.14 display data latch a series of registers carrying the display signal information. for ssd1800, there are 105 latches (80 + 25) for holding the data, which will be fed to the hv buffer cell and level selector to output the required voltage levels. 8.15 level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform. 8.16 hv buffer cell (level shifter) buffer cell work as a level shifter, which translates the low voltage output signal to the required, driving voltage. the output is shifted out with an internal frm clock that comes from the display timing generator. the voltage levels are given by the level selector that is synchronized with the internal m signal.
solomon systech mar 2004 p 24/42 rev 1.0 ssd1800 series 9 voltage generator circuit figure 12 - when built-in power supply is used av dd c1p c1n c2p c2n vf vl 6 vl 5 vl 4 vl 3 vl 2 av ss vd d - + gnd external power supply (vc, v f = 0,1) av dd c1p c1n c2p c2n vf vl6 vl5 vl4 vl3 vl2 av ss vd d gnd external power supply (vc, vf = 0,0) all capacitor is c2. c2 : 0.1 uf note: vc, vf = x 2 , x 0 in power control register c2 figure 13 when external power supply is used vdd 3x dc-dc converter 2x dc-dc converter remarks: (vc,vf = 1,1) note: vc, vf = bit x 2 and x 0 in the command of power control register; c1 = 2.2 f - 4.7 f x 2 is the bit of turns on/off of the internal voltage converter and regulator c2 = 0.1 f - 1 f x 0 is the bit of turns on/off of the voltage divider r1 and r2 = 500k-2.5m ohms r1 a vdd c1p c1n c2p c2n vl6 vf vl6 vl5 vl4 vl3 vl2 a vss + c2 + c2 vdd c1 + gnd r2 gnd a vdd c1p c1n c2p vl6 vf vl6 vl5 vl4 vl3 vl2 avss + c2 c2 + c1 + gnd r1 r2 gnd
ssd1800 series rev 1.0 p 25/42 mar 2004 solomon systech 10 frame frequency 1/17 duty
solomon systech mar 2004 p 26/42 rev 1.0 ssd1800 series 11 command table table 8 - command table d/c hex d7 d6 d5 d4 d3 d2 d1 d0 command description 0 02 0 0 0 0 0 0 1 0 return home ddram address is set to 00h from address counter and the cursor returns to 00h position the contents of ddram are not changed. 0 08 ? 0b 0 0 0 0 1 0 x1 x0 set double height mode x 1x0 = 00: normal display (por) x 1x0 = 01: com0 - com15 is double height x 1x0 = 10/11: normal display 0 0c ? 0f 0 0 0 0 1 1 x1 x0 set power save mode / oscillator control x 0 = 0: power save off (por) x 0 = 1: power save on x 1 = 0: oscillator off (por) x 1 = 1: oscillator on 0 10 ? 13 0 0 0 1 0 0 x1 x0 function set x 0 = 0: cgrom is selected (por) x 0 = 1: cgram is selected x 1 = 0: com0 -> com15 (por) x 1 = 1: com15 -> com0 0 18 ? 1b 0 0 0 1 1 0 x1 x0 set display start line x 1x0 = 00: ddram line 1 shows at the first line of lcd (por). x 1x0 = 01: ddram line 2 shows at the first line of lcd. x 1x0 = 10: ddram line 3 shows at the first line of lcd. x 1x0 = 11: ddram line 4 shows at the first line of lcd. 0 1c ? 1d 0 0 0 1 1 1 * x0 set bias control x 0 = 0: 1/5 bias (por) x 0 = 1: 1/4 bias 0 20 ? 27 0 0 1 0 0 x2 x1 x0 set power control register x 0 = 0: turns off the voltage divider (por) x 0 = 1: turns on the voltage divider x 1 : don?t care x 2 = 0: turns off the internal voltage converter and regulator (por) x 2 = 1: turns on the internal voltage converter and regulator 0 28 ? 2f 0 0 1 0 1 x2 x1 x0 set display control x 0 = 0: turns off the display (por) x 0 = 1: turns on the display x 1 = 0: blink off (por) x 1 = 1: blink on x 2 = 0: cursor off (por) x 2 = 1: cursor on 0 80 ? ff 1 x6 x5 x4 x3 x2 x1 x0 set dd/cgram address ddram/ cgram address range: ddram: 00h - 3fh cgram: 40h - 7fh 0 40 ? 5f 0 1 0 x4 x3 x2 x1 x0 set iconram address / contrast control iconram address range / contrast control register: iconram: 00h - 0fh contrast control register: 10h te: 11h (test byte) 0 00 0 0 0 0 0 0 0 0 nop command for no operation 0 30 0 0 1 1 * * * * set test mode reserved for ic testing. do not use note: 1. patterns other than that given in command table are prohibited to enter to the chip as a command. otherwise, unexpected resu lt will occur. 2. ?*? : don?t care.
ssd1800 series rev 1.0 p 27/42 mar 2004 solomon systech data read/ write to read data from the internal memories (ddram/ cgram/ iconram), input high to r/ w( wr ) pin and d/ c pin for 6800-series parallel mode, low to e( rd ) pin and high to d/ c pin for 8080-series parallel mode. no data read is provided for serial mode. in normal mode, address counter will be increased by one automatically after each data read. a dummy read is required before the first data read. see figure 4 in functional description. to write data to the internal memories (ddram/ cgram/ iconram), input low to r/ w( wr ) pin and high to d/ c pin for 6800-series and 8080-series parallel mode. for serial interface, it will always be in write mode. address counter will be increased by one automatically after each data write.
solomon systech mar 2004 p 28/42 rev 1.0 ssd1800 series 12 command descriptions 12.1 return home return home instruction field makes cursor return home. ddram address is set to 00h from address counter and the cursor returns to 00h position. the contents of ddram are not changed. 12.2 set double height mode this command increases the height of one character line from 8 to 16 dots. if the number of com signal needed exceeds the existing com signal, the last character line will not be displayed. it will happen at following case: 1. for x 1 x 0 = 01, where com0-com15 is double height. the 2nd line will not be displayed. figure 14? function set command (x 1 x 0 = 00) figure 15 - com0 ~ com15 is a double height line in function set command (x 1 x 0 = 01)
ssd1800 series rev 1.0 p 29/42 mar 2004 solomon systech 12.3 set power save mode / oscillator control to enter standby or sleep mode, it should be done by turning off the internal oscillator and turning on the power save control bit. the corresponding control bits are x 1 x 0 = 01. in order to put the system into low power consumption mode, internal voltage converter, voltage regulator and voltage divider should also be turned off by using power control register. after putting the system into power save mode, the following status will be entered: 1. internal oscillator and lcd power supply circuits are stopped. 2. segment and common drivers output av ss level. 3. the display data and operation mode before sleep are held. all the internal circuit is stopped. 12.4 function set this command sets 2 functions on the system. they are com shift direction (left or right) and cgrom/ cgram character area select. 12.5 set display start line this command is to set display start line register to determine starting address of display data ram to be displayed by selecting a value from 0 to 3. with the value equals to 0, the display will start from address (00h-0fh). with the value equals to 1, the display will start from address (10h-1fh). with the value equals to 2, the display will start from address (20h-2fh). with the value equals to 3, the display will start from address (30-3fh). 12.6 set bias control bias ratio 1/4 or 1/5 could be set using this command. when changing the number of line display, the bias ratio also needs to be adjusted to make display contrast consistent. 12.7 set power control register this command turns on / off the various power circuits associated with the chip which including regulated dc-dc converter and voltage divider. 12.8 set display control this command provides 3 display functions. it turns on/off of the cursor, blink and display. when both cursor and blink control bit set high, the driver make lcd alternate between inverting display character and normal display character at the cursor position with about a half second. on the contrary, if cursor control bit is low, only a normal character is displayed regardless of blink control bit.
solomon systech mar 2004 p 30/42 rev 1.0 ssd1800 series x 2 , x 1 display state 1, 0 (cursor mode) 1, 1 (blinking mode) 0, 0 0, 1 figure 16 - display attributes
ssd1800 series rev 1.0 p 31/42 mar 2004 solomon systech 12.9 set dd/ cgram address before writing/ reading data into/ from the ram, set the address by ram address set instruction. next, when data are written/ read in succession, the address is automatically increased by1. after accessing 7fh, the address is 00h. table 9 - dd/ cgram address mapping address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h ddram line 1 (00h - 0fh) 10h ddram line 2 (10h - 1fh) 20h ddram line 3 (20h - 2fh) 30h ddram line 4 (30h - 3fh) 40h cgram (pattern 0) cgram (pattern 1) 50h cgram (pattern 2) cgram (pattern 3) 60h cgram (pattern 4) cgram (pattern 5) 70h cgram (pattern 6) cgram (pattern 7)
solomon systech mar 2004 p 32/42 rev 1.0 ssd1800 series 12.10 set iconram address set before writing/ reading data into/ from the iconram, set the address by iconram address set instruction. next, when data are written/ read in succession, the address is automatically increased by 1. the 5 icons at a time can blink if blinking is enabled. the blink attributes of icon are the same as the cursor blink. for accessing dd/ cgram, the dd/ cgram address set instruction should be set before. after accessing 0fh, the address of iconram address is 00h. the iconram address ranges are 00h-0fh. table 10 - iconram address mapping address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h iconram (00h - 0fh) 10h c c r t e reserved 12.11 set contrast control register set the contrast control register (ccr) by iconram address set instruction. next, data are written to the ccr. the default value of ccr is (00000). te: test mode register (do not use) (11h) when the ccr and te registers are written, the address counter is not increased. 12.12 nop a command causing no operation. 12.13 set test mode this command forces the driver chip into its test mode for internal testing of the chip. under normal operation, user should not use this command.
ssd1800 series rev 1.0 p 33/42 mar 2004 solomon systech 13 maximum ratings table 11 - maximum ratings (voltage reference to vss) symbol parameter value unit av dd, dv dd supply voltage -0.3 to +4.0v v vl6 vlcd voltage -0.3 to +6.5v v v in input voltage v ss -0.3 to v dd +0.3 v t a operating temperature -30 to +85 c t stg storage temperature range -65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and vl6 be constrained to the range v ss < or = (v in) < or = v dd. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected.
solomon systech mar 2004 p 34/42 rev 1.0 ssd1800 series 14 dc characteristics table 12 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, ta = -30 to 85c.) symbol parameter test condition min typ max unit dvdd avdd logic and analog circuit supply voltage range (absolute value referenced to dvss and avss) 2.4 2.7 3.6 v idd1 idd2 isb display operation supply current drain access operation from mpu supply current drain standby mode supply current vdd = 3v, ta = 25c vlcd = 5.8v without load no access from mpu vdd = 3v, ta = 25c fcyc = 200khz current no load oscillator off power save on - - - - - - 85 500 5 a a a v lcd vl6 lcd driving voltage input voltage regulator output vlcd = vl6 - vss ta = 25c, c = 1uf 4 4 - - 5.8 5.8 v v vih vil logic high input voltage logic low input voltage 0.8*dvdd 0 - - dvdd 0.2*dvdd v v voh vol vl6 vl6 logic high output voltage logic low output voltage lcd driving voltage source (vl6) lcd driving voltage source (vl6) ioh = -1ma, vdd = 2.4v iol = 1ma, vdd = 2.4v regulator enable (vl6 voltage depends on contrast control/ external resistors network) regulator disable dvdd ? 0.4 - avss - 0.5 - - - - floating - 0.4 5.8 - v v v v v l 6 v l 5 v l4 v l3 v l2 v l 6 v l 5 v l4 v l3 v l2 lcd display voltage output (v l5 , v l4 , v l3 , v l2 ) lcd display voltage output (v l5 , v l4 , v l3 , v l2 ) voltage reference to av ss , bias divider enabled, 1:a bias ratio voltage reference to av ss , external voltage generator, bias divider disable - - - - - v l 5 v l4 v l3 v l2 v ss v l6 (a-1)/a * v l6 (a-2)/a * v l6 2/a * v l6 1/a * v l6 - - - - - - - - - - 5.8 v l 6 v l 5 v l4 v l3 v v v v v v v v v v i oh i ol i oz logic high output current source logic low output current drain logic output tri-state current drain source vout = vdd - 0.4v vout = 0.4v 50 - -1 - - - - -50 1 a a a i il / i ih logic input current -1 - 1 a c in logic pins input capacitance - 5 7.5 pf vref voltage regulator reference voltage 1.94 2 2.06 v
ssd1800 series rev 1.0 p 35/42 mar 2004 solomon systech 15 ac characteristics table 13 - ac characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, ta = -30 to 85c.) symbol parameter test condition min typ max unit f frm frame frequency internal oscillator v dd = 3v, t a = 25 c 67.5 75 90 hz table 14 - 6800-series mpu parallel interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 650 - - ns t as address setup time 60 - - ns t ah address hold time 30 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 50 - - ns t dhr read data hold time 50 - - ns t oh output disable time - - 70 ns t acc access time - - 100 ns e( rd ) low pulse width (read) 150 - - ns pw el e( rd ) low pulse width (write) 150 - - ns e( rd ) high pulse width (read) 450 - - ns pw eh e( rd ) high pulse width (write) 450 - - ns t r rise time - - 25 ns t f fall time - - 25 ns figure 17? 6800-series mcu parallel interface waveform
solomon systech mar 2004 p 36/42 rev 1.0 ssd1800 series table 15 - 8080-series mpu parallel interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 650 - - ns t as address setup time 60 - - ns t ah address hold time 30 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 50 - - ns t dhr read data hold time 50 - - ns t oh output disable time - - 70 ns t acc access time - - 100 ns wr low pulse width (read) 450 - - ns pw wrl wr low pulse width (write) 450 - - ns wr high pulse width (read) 150 - - ns pw wrh wr high pulse width (write) 150 - - ns t r rise time - - 25 ns t f fall time - - 25 ns figure 18? 8080-series mcu parallel interface waveform
ssd1800 series rev 1.0 p 37/42 mar 2004 solomon systech table 16 - serial interface timing characteristics (vdd - vss = 2.4 to 3.6v, ta = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 1000 - - ns t as address setup time 50 - - ns t ah address hold time 300 - - ns t css chip select setup time 150 - - ns t csh chip select hold time 700 - - ns t dsw write data setup time 50 - - ns t dhw write data hold time 50 - - ns t clkl clock low time 300 - - ns t clkh clock high time 300 - - ns t r rise time - - 25 ns t f fall time - - 25 ns figure 19? serial interface characteristics
solomon systech mar 2004 p 38/42 rev 1.0 ssd1800 series 16 application examples figure 20- application circuit: external regulator with internal divider mode (8-bit 6800 mode) ssd1800 ic 16 mux (die face ip) seg79?????????????????????????????seg0 comi1 . . . com15 com14 : : com9 com8 com7 com6 com5 : : . . com0 comi0 seg0??????????????????????seg79 display panel size 80 x 16 + 1 icon line com8 com9 : : com14 com15 . . comi1 comi0 com0 com1 : .. . . . . : com6 com7 d0-d7 dvss & avss[gnd] vdd=3.0v avss 0.1uf + dvdd vl2 vl3 vl4 vl5 vl6 a vdd external power supply logic pin connections not specified above: pins connected to dvdd: c68/ 80 , p/ s , dl, dirs pins connected to dvss: ref, clk e(/rd) /cs /res d/#c r/w (#wr)
ssd1800 series rev 1.0 p 39/42 mar 2004 solomon systech logic pin connections not specified above: pins connected to dvdd: dl, dirs pins connected to dvss: ref, clk, p/ s, r/ w( wr ), e(/rd), c68/ 80 , d5-d0 figure 21 - application circuit: all internal power mode with 2x regulated dc-dc converter (serial mode) ssd1800 ic 16 mux (die face ip) seg79?????????????????????????????seg0 comi1 . . com15 com14 : : com9 com8 com7 com6 com5 : : com0 comi0 seg0??????????????????????seg79 display panel size 80 x 16 + 1 icon line com8 com9 : : com14 com15 : : . . comi1 comi0 com0 com1 : : . . . . com6 com7 sck (d6) sda (d7) dvss & avss[gnd] avdd vdd = 3.0v dvdd vl2 vl3 vl4 vl5 vl6 a vdd vl6 c1n c1p c2p r1 r2 vf a vss note: it is recommended to use 2x regulated dc-dc converter to reduce the current consumption under certain of condition. e.g. av dd /dv dd = 3.0v and v lcd (lcd driving voltage) = 5.0v. +c1 c2 c2 c1: 2.2 -4.7 uf c2: 0.1-1uf /cs /res d/#c + + remarks: r1 and r2 = 500k-2.5m ohms
solomon systech mar 2004 p 40/42 rev 1.0 ssd1800 series logic pin connections not specified above: pins connected to dvdd: p/ s , dl, dirs pins connected to dvss: ref, clk, and c68/( 80 ) figure 22- application circuit: all internal power mode with 3x regulated dc-dc converter (8-bit 8080 mode) ssd1800 ic 16 mux (die face ip) seg79?????????????????????????????seg0 comi1 . . com15 com14 : : com9 com8 com7 com6 com5 : : com0 comi0 seg0??????????????????????seg79 display panel size 80 x 16 + 1 icon line com8 com9 : : com14 com15 : : comi1 comi0 com0 com1 : : . . com6 com7 d0-d7 e(/rd) /cs /res dvss & avss[gnd] d/#c avdd vdd = 3.0v dvdd vl2 vl3 vl4 vl5 vl6 a vdd vl6 c1n c1p c2n c2p r1 r2 vf a vss r/w (#wr) +c1 c2 c2 c1: 2.2 -4.7 uf c2: 0.1-1uf + + remarks: r1 and r2 = 500k-2.5m ohms
ssd1800 series rev 1.0 p 41/42 mar 2004 solomon systech recommended initializing of ssd1800 figure 23- recommended initializing of ssd1800 dv dd /av cc -dv ss /av ss power on end of initialization send reset pulse to the res pin. (recommended minimum reset pulse width is 10ms) waiting for 10usec command input 1. function set (000100x1x0) 2. contrast control register setup 3. power save (power save off; osc on) 4. power control (turns on the internal regulator and turns on the internal divider) command input 5. ram address set data input 6. data writing (ram clear) (ddram=20h, cg/iconram=00h) command input 7. display control (turns on the display) (there is an auto mask off period ~ 260ms) note: a t instructions 1-6, the minimum clock cycle time is 650ns for ppi. for details, pls refe r to the ssd1800 datasheet ?ac characteristics?. a t 5 and 6, the internal ram should be cleared. to clear ddram, set address at 00h (firs t ddram) and then write 20h (space character code) 64times. to clear cgram, set address at 40h (firs t cgram) and then write 00h (null data) 64 times to clear iconram, set conram address at 00h (first iconram) and then write 00h (null data) 16 times no delay between each command/data input under ideal timing situation (no time shift in any signals, refer to page 32 fo r details)
solomon systech mar 2004 p 42/42 rev 1.0 ssd1800 series solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential or incidental damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typica l? must be validated for each customer application by customer?s technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regard ing the design or manufacture of the part. http://www.solomon-systech.com

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